1. Field of the Invention
The present invention relates to a semiconductor structure and fabrication method thereof, and particularly, to a lateral double-diffused metal oxide semiconductor and fabrication method thereof.
2. Description of the Related Art
Single-chip systems have been developed, which comprise controllers, memory devices, low-voltage (LV) circuits and high-voltage (HV) power devices. For example, double-diffused metal oxide semiconductor (DMOS) transistors, which are frequently used as conventional power devices, operate with low on-resistance and high voltage. Moreover, by using very-large-scale integration (VLSI) technology, a high-voltage lateral double-diffused metal oxide semiconductor (LDMOS) may have higher on-resistance than a commonly used vertical double-diffused metal oxide semiconductor (VDMOS).
When designing a transistor, high breakdown voltage and low on-resistance are two main concerns. Recently, reduced surface electrical field (RESURF) technology has been adopted in fabrication of a LDMOS. FIG. 1 is an N-type LDMOS device using a RESURF concept illustrated in U.S. Pat. No. 6,773,997 B2. An N-type well 413 is extended from a channel region 415 to an N+-type drain 406. A uniformly doped flat P-type region 408 is formed on the N-type well 413. When the device operates with an applied voltage, the N-type well 413 functions as a carrier drift region, and the P-type region 408 functions as a RESURF layer. U.S. Pat. No. 6,773,997 B2 further describes a device having a plurality of layers of uniformly doped flat P-type regions 408, 402, as shown in FIG. 2.
Referring to FIG. 2, the N-type well 413 can be easily depleted since it is disposed between the flat P-type region 408, 402 and the P-type substrate 401. Therefore, the N-type well 413 can be formed with a high dosage of dopant to reduce on-resistance of a device made therefrom. However, for the LDMOS device in off-state, electrical fields therein are concentrated around the N+-type drain 406. Thus, an electrical field (or current) crowding effect occurs, resulting in a decrease in breakdown voltage and switching speed. While the doping concentration of the N-type well 413 may be decreased to increase the degree of depleting the N-type well 413, resulting in a higher breakdown voltage, the on-resistance of the LDMOS device would also increase. Thus, a semiconductor structure and fabrication method for UHV devices having a high breakdown voltage and low on-resistance is desired.